Advances in Embedded and Fan-Out Wafer Level Packaging Technologies, 組み込みおよびファンアウト・ウェハレベル・パッケージング技術の進歩, 9781119313984, 978-1-119-31398-4【電子書籍 / 1ユーザー】
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Description
Embedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.
Filled with contributions from some of the field's leading experts,Advances in Embedded and Fan-Out Wafer Level Packaging Technologies begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.
- Discusses specific company standards and their development results
- Content relates to practice as well as to contemporary and future challenges in electronics system integration and packaging
Contents:
1 History of Embedded and Fan-Out Packaging Technology
2 FO-WLP Market and Technology Trends
3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform
4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology
5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging
6 M-Series Fan-Out with Adaptive Patterning
7 SWIFTR Semiconductor Packaging Technology
8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration
9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology
10 Embedding of Power Electronic Components: The Smart p2 Pack Technology
11 Embedded Die in Substrate (Panel-Level) Packaging Technology
12 Blade: A Chip-First Embedded Technology for Power Packaging
13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology
14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP)
15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging
16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging
17 Process and Equipment for eWLB: Chip Embedding by Molding
18 Tools for Fan-Out Wafer-Level Package Processing
19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings
21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages
22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems