JEDEC規格 JEP122H Revision H, 2016: Failure Mechanisms and Models for Semiconductor Devices
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Description
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method.
The models apply primarily to the following:
a) Aluminum (doped with small amounts of Cu and/or Si) and copper alloy metallization
b) Refractory metal barrier metals with thin anti-reflection coatings
c) Doped silica or silicon nitride interlayer dielectrics, including low-dielectric-constant materials
d) Poly silicon or “salicide” gates (metal-rich silicides such as W, Ni & Co to decrease resistivity)
e) Thin SiO2 gate dielectric
f) Silicon with p-n junction isolation
g) Tin Whisker Growth Kinetics
h) Printed Circuit Board Ionic Mobility